[AI Infrastructure Dissection] Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM): Foundry Sovereignty, the AI Supercycle, and the Architecture of Global Capacity

AI Infrastructure Briefing Series — No. 10

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED (NYSE: TSM · TWSE: 2330)

NVIDIA's Rubin Has to Be Real Somewhere: TSMC FY2025 and Q1 2026

Sources: SEC EDGAR (TSM Form 20-F FY2025 · 6-K series 2025–2026) · LSEG StreetEvents Q1 2026 Earnings Call Transcript · May 2026

The Five Things That Matter

Most people tracking AI stocks focus on Nvidia, Apple, or AMD. TSMC is the company that none of them can function without. It is the only factory on earth capable of building the most advanced AI chips at commercial scale. Here is what matters most.

 

1. TSMC is the only manufacturer that can build the most advanced AI chips. Nvidia, Apple, AMD, Qualcomm — they design chips but cannot build them. TSMC builds them on a contract basis, using manufacturing processes so complex that no competitor has been able to match them at the most advanced levels. In 2025 it manufactured 12,682 distinct products for 534 customers using 305 different production processes. FY2025 revenue: US$122.4 billion.

 

2. Revenue grew 35.9% in a single year, almost entirely because of AI. The segment that covers AI accelerators, data centre processors, and networking chips — High Performance Computing — grew 48% in 2025 and now accounts for 58% of all revenue, up from 43% just two years earlier. Gross margin — the share of each revenue dollar kept after paying manufacturing costs — reached 59.9%, a record at the time.

 

3. Q1 2026 broke that record immediately: 66.2% gross margin. For every dollar of revenue, TSMC kept 66 cents after paying all production costs. That is among the highest manufacturing margins of any large company in the world, and it exceeded the company’s own guidance by 1.2 percentage points. It reflects a combination of more advanced chip production, near-full factory utilisation, and pricing power that comes with having no credible competition on the most advanced processes.

 

4. The most advanced process in history, N2, entered volume production in Q4 2025. N2 uses a new transistor design that allows chips to run faster while using less power than any previous generation. Demand is so strong that TSMC announced a global expansion of the generation before it — 3-nanometer, already in production since 2022 — with new factories being built in Taiwan, Arizona, and Japan to meet orders it cannot currently fill. The generation after N2, called A14, is on track for 2028.

 

5. The capital expenditure plan is unprecedented: $52–56 billion in 2026 alone. That is more than TSMC spent in the three previous years combined. In the United States, the total committed investment has reached US$165 billion — six new fabs plus packaging and R&D facilities in Arizona — with Apple, Nvidia, AMD, Broadcom, and Qualcomm named as the intended customers. A US$20 billion capital injection into the Arizona subsidiary was approved in May 2026.

 

Key Metrics at a Glance

FY2025 Net Revenue

US$122.4B

+35.9% Y/Y in USD

FY2025 Net Income (IASB)

US$54.1B

EPS NT$65.47 diluted

FY2025 Gross Margin

59.9%

+3.8pp vs FY2024; record

FY2025 Operating Margin

50.8%

+5.1pp vs FY2024

FY2025 R&D Spend

NT$246.4B

6.5% of revenue

FY2025 CapEx

US$40.9B

+33.1% Y/Y

Q1 2026 Net Revenue

US$35.9B

+40.6% Y/Y; +8.4% QoQ

Q1 2026 Gross Margin

66.2%

All-time record; beat guidance

Q1 2026 EPS (Diluted)

NT$22.08

US$3.49 ADR; +58.3% Y/Y

2026 CapEx Guidance

US$52–56B

Towards high end

Cash (Mar 31, 2026)

US$106B

TWD3.4 trillion

2026 Revenue Outlook

>30%

Raised from “close to 30%”

Sources: TSMC, Form 20-F FY2025 (Apr 16, 2026); 6-K Q1 2026 Earnings Release (Apr 16, 2026); 6-K Q1 2026 Earnings Presentation (Apr 16, 2026); 6-K May 2026 Board Resolutions (May 12, 2026). Net income on IASB-IFRS basis. USD revenue at weighted-average NT$31.11 per US$1.00 (FY2025).

I.  What TSMC Does▼

I. What TSMC Does: The World’s Contract Chip Manufacturer

TSMC — Taiwan Semiconductor Manufacturing Company — was founded in 1987 as a joint venture between the Taiwanese government and private investors. It pioneered a business model that has since become the backbone of the entire consumer electronics industry: the pure-play foundry. A foundry, in the semiconductor world, is a factory that manufactures chips designed by other companies. TSMC does not design its own chips, does not sell products under its own brand, and does not compete with the customers it serves. That last point — the non-competition principle — is the foundation of its commercial relationships. Companies like Apple and Nvidia share extraordinarily sensitive chip designs with TSMC because they know TSMC will never use that information to build a competing product. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

The scale at which TSMC operates is difficult to overstate. In 2025, it deployed 305 distinct manufacturing processes and produced 12,682 different products for 534 customers worldwide. As of February 28, 2026, it operated 23 production facilities across Taiwan, the United States, China, and Japan, including one 150mm fab, six 200mm fabs, nine 300mm fabs — the industry-standard size for advanced production — and seven advanced packaging facilities. Annual production capacity exceeded 17 million 12-inch equivalent wafers, the standard unit for measuring semiconductor output. The company employed 90,557 people at December 31, 2025, with approximately 86% based in Taiwan. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Items 4 and 6)

 

Five End Markets

TSMC organises its business around five types of customer application. High Performance Computing (HPC) is the largest and fastest-growing: it covers the AI accelerators (the chips inside Nvidia GPUs and custom AI processors from Apple, Google, Amazon, and others), data centre central processing units, and the networking chips that connect servers together. Smartphone covers the application processors inside mobile phones — the chips that run the operating system, camera software, and wireless connectivity. Internet of Things (IoT) covers edge-computing chips for connected devices — smart home equipment, industrial sensors, wearables. Automotive covers chips for advanced driver-assistance systems, electric vehicle control units, and in-vehicle infotainment. Digital Consumer Electronics, the smallest segment, covers chips for TVs and premium display devices. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

Advanced Packaging: From the Chip to the System

Beyond manufacturing individual chips, TSMC has become a leading provider of advanced packaging — the technology that combines multiple chips into a single unified package, allowing them to communicate with each other at speeds impossible over conventional circuit boards. Its CoWoS® technology (Chip on Wafer on Substrate) places multiple chips side by side on a silicon bridge, giving them extremely fast connections and shared memory access. This is how Nvidia’s H100 and B100 AI accelerators — which combine a computing chip with several memory chips — are assembled. CoWoS capacity is described by management as “very tight”; advanced packaging revenue was close to 10% of total wafer revenue in 2025 and expected to grow above that in 2026. (LSEG StreetEvents 2026, p. 17)

 

Terms Explained

 

Pure-Play Foundry. A semiconductor manufacturer that fabricates chips exclusively for other companies using their proprietary designs, without designing or selling its own chip products. The pure-play model allows companies that design chips — fabless companies — to focus entirely on design without building expensive factories. TSMC's non-competition principle is the commercial foundation of the model: customers share sensitive designs because TSMC will never use them to build competing products.

 

Fabless Company. A semiconductor firm that designs chips but outsources all manufacturing to a foundry. Nvidia, Apple, AMD, Qualcomm, and Broadcom are all fabless; they employ chip designers but own no factories. The term contrasts with Integrated Device Manufacturers (IDMs) like Intel, which both design and manufacture their own chips.

 

Wafer. A thin, round disc of silicon on which hundreds or thousands of chips are simultaneously printed using photographic exposure and chemical etching. A 300mm (12-inch) wafer is the standard size for the most advanced chip production. The more chips that fit on a wafer, and the higher the proportion of chips that work correctly (the 'yield'), the more profitable each wafer run becomes.

 

Advanced Packaging / CoWoS®. Traditional chips are manufactured individually and then connected via a circuit board. Advanced packaging skips the circuit board for the critical connections: it places multiple chips on a shared silicon or glass substrate, with microscopic copper connections running directly between them. This allows much higher data transfer speeds and lower power consumption than board-level connections. CoWoS (Chip on Wafer on Substrate) is TSMC's leading implementation, used by Nvidia for its AI accelerators.

 

II.  FY2025 Financials▶

II. FY2025 Financial Performance: The AI Inflection Takes Hold

Annual Revenue and Gross Margin Trend (FY2023–FY2025)

 

Sources: TSMC 2026c, Item 5. Bars = net revenue in NT$ billions (left axis). Amber line = gross margin % (right axis).

Revenue by Platform and Technology Node (FY2023–Q1 2026)

 

Source: Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4 (FY2023–2025 annual); 2026b (Q1 2026). Platform chart. Click “Tech Nodes” tab for node breakdown.

Revenue and the Platform Shift

TSMC recorded net revenue of NT$3,809,054 million — US$122.42 billion — in FY2025, up 35.9% in US dollar terms from FY2024. That growth rate is the compound effect of two forces: wafer shipments grew sharply, and the mix shifted toward advanced chips, which carry higher prices per wafer than older-generation products. Wafer shipments grew from approximately 13 million to approximately 15 million 12-inch equivalent wafers. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

The revenue split by end market tells the AI story directly. The High Performance Computing segment — AI accelerators, data centre processors, networking chips — grew 48% in FY2025 to NT$2,192,931 million (US$70.5 billion), and its share of total revenue rose from 43% in FY2023 to 51% in FY2024 to 58% in FY2025. Smartphone grew a more modest 11% to 29% of revenue. Automotive expanded 34% to 5%. The concentration of growth in HPC is not incidental: it reflects the trillion-dollar expansion of AI infrastructure that is the primary demand driver in global semiconductor markets. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

Geographically, North America now accounts for 75% of TSMC’s revenue — up from 70% in FY2024 — at NT$2,875,270 million. US-headquartered AI and technology companies drove a 42% increase in North American orders year-on-year. China contracted to 9% of revenue as US export controls progressively restricted TSMC’s ability to ship the most advanced chips to that market. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

Technology Mix: The Margin Engine

The shift toward more advanced chips within TSMC’s product mix is the primary mechanical driver of its rising profitability. Older chip generations — 28-nanometer, 40-nanometer, 65-nanometer — are commoditised and carry lower prices. Newer generations — 3-nanometer, 5-nanometer — are available from only one or two manufacturers worldwide and carry higher prices. In FY2025, 3-nanometer chips accounted for 24% of wafer revenue (up from 6% in FY2023), 5-nanometer for 36%, and 7-nanometer for 14%. Collectively, chips at 7-nanometer and below — what TSMC calls “advanced technologies” — were 74% of wafer revenue, up from 69% in FY2024 and 58% in FY2023. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

Wafer Revenue by Technology Node — FY2023–Q1 2026

 

Source: Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5 (FY2023–2025); 2026e (Q1 2026). ≥90nm is the residual after all named nodes; sum verified at 100% for each period.

Profitability: Margins That Reflect Pricing Power

Gross margin — the share of revenue remaining after paying the direct cost of manufacturing — reached 59.9% in FY2025, up from 56.1% in FY2024 and 54.4% in FY2023. Operating margin — gross margin after also deducting R&D, selling, and administrative expenses — reached 50.8%, up from 45.7%. These are extraordinary figures for a manufacturing company. For comparison, most major industrial manufacturers operate at gross margins of 30–45%. TSMC’s 59.9% reflects the combination of advanced-node pricing power and the operating leverage of a business where adding more revenue requires relatively little additional overhead. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

Net income attributable to shareholders of the parent was NT$1,697,604 million (US$54.12 billion) on the IASB-IFRS basis used in the Form 20-F, with diluted earnings per share of NT$65.47. The Taiwan-IFRS basis — used in domestic quarterly reporting — gives a slightly higher figure of NT$1,717,882 million (EPS NT$66.25); the difference of NT$20,278 million arises entirely from a timing difference in how retained-earnings tax is recognised under the two standards and has no cash effect. Income tax expense rose 39.6% to NT$346,530 million — a direct consequence of higher taxable earnings. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

Cash Generation and the Balance Sheet

Operating cash flow was NT$2,274,976 million (US$72.52 billion) in FY2025, up 24.6% from FY2024. Capital expenditure was NT$1,272,411 million (US$40.90 billion), up 33.1%, directed primarily at expanding N2, N3, and N5 process capacity and building advanced packaging infrastructure. Free cash flow — the cash left after capital spending — was NT$1,002,570 million. Even while spending at an extraordinary rate, TSMC generated more than US$32 billion in surplus cash. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

The cash and marketable securities balance rose to NT$3,068,595 million (US$97.82 billion) at December 31, 2025, a 26.7% increase. Long-term debt was NT$1,032,988 million (US$32.93 billion), comprising corporate bonds at fixed interest rates of 0.41% to 4.63%. The balance sheet is healthy: TSMC is funding a global expansion programme of extraordinary scale entirely from its own cash generation, without financial stress. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 5)

 

Research and development spending was NT$246,427 million (US$7.86 billion), representing 6.5% of net revenue and a 20.7% year-on-year increase. The bulk of this goes toward developing the next two generations of process technology — 10-angstrom, 14-angstrom, and 16-angstrom nodes — while the current generation (N2) has only just entered production. That gap between production generation and research frontier is what maintains TSMC’s multi-year competitive lead. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

Management has outlined the company’s long-term financial targets: from 2024 to 2029, compound annual revenue growth is expected to approach 25% in US dollar terms; long-term gross margin is guided at 56% and higher through the cycle; and return on equity — the profit generated per dollar of shareholders’ investment — is targeted at the high 20% range through the cycle. (Taiwan Semiconductor Manufacturing Company Limited 2026a)

 

Terms Explained

 

Gross Margin. Revenue minus the direct cost of manufacturing (materials, direct labour, factory overhead), divided by revenue. TSMC's 59.9% gross margin in FY2025 means it kept NT$0.599 of every NT$1.00 of revenue after paying for the raw materials, chemicals, and factory labour needed to make each wafer. Higher margins reflect more advanced chip production, which commands higher prices.

 

Operating Margin. Gross profit minus operating expenses (R&D, selling costs, administrative overhead), divided by revenue. Where gross margin measures manufacturing profitability, operating margin measures the efficiency of the entire business. TSMC's 50.8% operating margin means it kept NT$0.508 per NT$1.00 of revenue as operating profit — before interest costs and taxes.

 

Free Cash Flow (FCF). Operating cash flow (cash generated from running the business) minus capital expenditure (cash spent on factories, equipment, and physical assets). FCF is the money a company is genuinely free to use for dividends, debt repayment, or investments. TSMC generated NT$1,002,570 million (US$32.3 billion) in FCF in FY2025 despite spending NT$1,272,411 million on capital investment.

 

CAGR (Compound Annual Growth Rate). The annualised rate at which a value would need to grow each year to get from its starting point to its ending point over a multi-year period. A 25% CAGR from 2024 to 2029 means the revenue figure needs to multiply by approximately 3.1 times over five years.

 

IASB-IFRS vs Taiwan-IFRS. TSMC prepares two sets of financial statements: one under Taiwan IFRS (for domestic reporting) and one under IASB-issued IFRS (for the US SEC Form 20-F). The only difference in FY2025 is the timing of recognising retained-earnings tax under Taiwanese law. The IASB basis shows slightly lower net income (NT$1,697,604 million vs. NT$1,717,882 million), with no cash impact.

 

III.  Q1 2026 Results & Outlook▶

III. Q1 2026: Record Margins and a Raised Outlook

TSMC opened 2026 with its strongest quarter on record. Revenue was NT$1,134,103 million (US$35.90 billion), up 8.4% from Q4 2025 and up 40.6% year-on-year in US dollar terms. This slightly exceeded the US$34.6–35.8 billion guidance range set at the January earnings call, driven by demand for leading-edge process technologies running above the company’s own expectations. (Taiwan Semiconductor Manufacturing Company Limited 2026e)

 

Gross margin reached 66.2% — a 3.9 percentage point improvement from Q4 2025 and 7.4 percentage points above Q1 2025. The three main drivers were: cost improvements from more efficient factory operations; higher overall factory utilisation (more revenue was produced from the same fixed cost base); and a more favourable exchange rate (the NT dollar weakened slightly against the US dollar). Crucially, the actual outcome exceeded the high end of the company’s own guidance by 1.2 percentage points (120 basis points — a basis point is one hundredth of a percentage point), because factory utilisation ran higher than forecast. (LSEG StreetEvents 2026, p. 3)

 

Quarter-on-Quarter Revenue and Gross Margin Trend

 

Source: TSMC 2026e (Q1 2026 Earnings Release, Apr 16, 2026). Bars = revenue NT$ billions (left axis). Amber line = gross margin % (right axis). Q1′25 gross margin calculated from release comparison table: NT$493,395M / NT$839,254M = 58.8%.

Operating margin was 58.1%, up 4.1 percentage points sequentially. Net profit margin was 50.5% — the first time in TSMC’s history that it has kept more than half of every revenue dollar as net income in a single quarter. Diluted earnings per share were NT$22.08 (US$3.49 per ADR unit — each ADR represents five ordinary shares), up 58.3% year-on-year. Annualised return on equity was 40.5%, well above the long-term target of high-20%. (Taiwan Semiconductor Manufacturing Company Limited 2026e)

 

Platform and Technology Mix

High Performance Computing grew 20% sequentially and accounted for 61% of Q1 2026 revenue — its highest-ever share. The sequential jump reflects the AI training and inference infrastructure investment cycle, where orders tend to be lumpy rather than smoothly distributed across quarters. Smartphone declined 11% sequentially (a normal Q1 seasonal pattern as consumer demand softens after the holiday period) to 26% of revenue. IoT grew 12% to 6%, Automotive fell 7% to 4%, and Digital Consumer Electronics grew 28% to 1%. (LSEG StreetEvents 2026, p. 3)

 

At the technology node level, 3-nanometer continued to grow: from 24% of annual wafer revenue in FY2025 to 25% in Q1 2026. Five-nanometer held at 36%. Seven-nanometer declined to 13%. Advanced technologies collectively were 74% of wafer revenue, consistent with FY2025’s annual figure. (Taiwan Semiconductor Manufacturing Company Limited 2026e)

 

Q2 2026 Guidance and the Full-Year Outlook

For Q2 2026, management guided revenue of US$39.0–40.2 billion — a 10% sequential increase at the midpoint and a 32% year-on-year increase. Gross margin is expected to be 65.5–67.5%, operating margin 56.5–58.5%. The Q2 guidance embeds a countervailing pair of forces: continued improvement from higher utilisation and cost efficiency, partially offset by the ramp costs of overseas fabs (it is more expensive to operate a new factory in the early months of production than an established one). The Q2 tax rate is expected to be approximately 20% due to a retained-earnings tax accrual; the full-year rate is guided at 17–18%. (Taiwan Semiconductor Manufacturing Company Limited 2026e; LSEG StreetEvents 2026, p. 3)

 

TSMC simultaneously raised its full-year 2026 revenue growth guidance from “close to 30%” to “above 30%” in US dollar terms, citing stronger-than-expected demand signals from cloud service providers and hyperscalers. Wendell Huang, CFO, confirmed that the 2026 capital expenditure budget is expected toward the high end of the US$52–56 billion range, meaning equipment deliveries and construction timelines have been accelerated to respond to demand. (LSEG StreetEvents 2026, p. 4)

 

An important profitability milestone for H2 2026: the 3-nanometer process, which has been in production since late 2022, is expected to cross the corporate average gross margin in the second half of the year. This is a normal maturation pattern: new process nodes begin life below average margins due to high initial depreciation and yield learning costs; as the technology matures, margins improve until they eventually exceed the corporate average. When N3 crosses that threshold, it will be a net positive for TSMC’s consolidated profitability. (LSEG StreetEvents 2026, p. 4)

 

At the May 12, 2026 Board of Directors meeting, the Board approved a Q1 2026 cash dividend of NT$7.00 per share (payable October 8, 2026), capital appropriations of approximately US$31,284 million for advanced technology capacity installation and fab construction, and a capital injection of not more than US$20 billion into TSMC Arizona. The appropriations and the Arizona injection are separate decisions; together they represent the specific project-level commitments that will deploy the annual capital budget. (Taiwan Semiconductor Manufacturing Company Limited 2026d)

 

Terms Explained

 

Basis Point (bp). One hundredth of one percentage point. 100 basis points = 1 percentage point. Used to describe small but financially meaningful changes in margins or interest rates. TSMC beat its Q1 gross margin guidance by 120 basis points — meaning its 66.2% actual outcome was 1.2 percentage points above the 65.0% high end of guidance.

 

Sequential Growth (QoQ). Quarter-over-quarter percentage change, comparing the most recent quarter to the immediately preceding one. TSMC's Q1 2026 revenue grew 8.4% sequentially from Q4 2025. Seasonal patterns mean Q1 is typically weaker than Q4 for the smartphone segment but stronger for data centre customers.

 

ADR (American Depositary Receipt). A certificate that trades on a US stock exchange and represents ownership of shares in a non-US company. Each TSMC ADR (NYSE: TSM) represents five ordinary shares. Q1 2026 diluted EPS of NT$22.08 per ordinary share translates to US$3.49 per ADR at the prevailing exchange rate.

 

Ramp Costs. The elevated costs incurred when a new factory or new process technology first enters production. Equipment must be calibrated, factory workers trained, supply chains established, and yields improved before a new facility reaches the same efficiency as a mature one. TSMC's overseas fabs in Arizona, Japan, and Germany all carry ramp costs that weigh on consolidated gross margin.

 

IV.  Technology & Global Expansion▶

IV. Technology Leadership and the Global Capacity Build-Out

TSMC’s competitive position rests on its ability to bring new process generations into volume production faster than any rival. The gap between what TSMC can manufacture today and what its closest competitors can match has, if anything, widened in recent years. Its latest process, N2, entered volume production in Q4 2025 — with confirmed good yields — at both the Hsinchu and Kaohsiung sites in Taiwan simultaneously. Demand is supported by both smartphone and AI/HPC customers. (LSEG StreetEvents 2026, p. 5)

 

N2: A New Transistor Architecture

N2 is TSMC’s first process to use “gate-all-around” (GAA) nanosheet transistors — a fundamentally different transistor structure from the FinFET technology used in every previous generation. Understanding the difference matters for understanding why N2 is significant. A transistor is the basic switch inside a chip: it controls whether electrical current flows (representing a “1”) or does not flow (representing a “0”). As transistors get smaller, they become harder to switch reliably because current can leak around the edges. FinFET technology, which wraps the controlling electrode (the “gate”) around three sides of the current channel, was introduced at 22nm to solve this problem. GAA technology goes further: the gate wraps around all four sides of a stack of thin horizontal sheets (the “nanosheets”), giving near-perfect electrical control.

 

FIGURE: Transistor Generation Comparison (cross-section perpendicular to current flow)

Compared with N3E — the mature 3-nanometer node it most directly follows — N2 offers a 10–15% speed improvement at the same power level, or a 20–30% reduction in power at the same speed, with chip density at least 1.15 times higher. These improvements translate directly into AI chips that are faster, run cooler, and pack more computing power into a smaller space. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

The N2 product family is deliberately structured for longevity. N2P, a performance-enhanced variant, and A16 — which adds a “backside power delivery network” that routes electrical power through the back of the chip rather than competing with data connections on the front — extend the commercial life of the N2 platform. A16 is expected to enter risk production (the final pre-volume validation stage) in 2026. C.C. Wei, TSMC’s Chairman and CEO, stated directly: “With our strategy of continuous enhancement, such as N2P and A16, we expect our N2 family to be another large and long-lasting node for TSMC.” (LSEG StreetEvents 2026, p. 5)

 

A14: The Generation After Next

At the Q1 2026 earnings call, TSMC disclosed for the first time the detailed specifications of A14 — the process generation that follows A16. A14 uses second-generation nanosheet transistors and targets another full-node jump in performance: 10–15% speed improvement at the same power as N2, or 25–30% power reduction at the same speed, with approximately 20% higher chip density. Technology development is described as “on track and progressing well”; both smartphone and HPC customers are already engaged. Volume production is scheduled for 2028. (LSEG StreetEvents 2026, p. 6)

 

The Global N3 Expansion: A Policy Reversal Driven by AI

The most strategically significant announcement at the Q1 2026 earnings call was TSMC’s decision to expand its 3-nanometer capacity globally — a reversal of previous policy. Historically, TSMC does not add capacity to a process node once it has reached its planned maximum. The AI demand for N3 chips — now spanning not just smartphones and traditional HPC but also HBM base dies (the logic chip at the base of a High Bandwidth Memory stack, used to co-ordinate the memory layers in AI servers) — exceeded all projections. TSMC announced three new N3 production sites: (LSEG StreetEvents 2026, p. 5)

 

Site	Status	Volume Production Target
Tainan, Taiwan (GIGAFAB cluster)	New fab announced; construction underway	H1 2027
Arizona, USA (Fab 21 Phase 2)	Construction complete; equipment installation	H2 2027
Kumamoto, Japan (JASM Fab 2)	Construction started October 2025	2028

Source: LSEG StreetEvents 2026, p. 5; Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4.

In addition to new fabs, TSMC is converting 5-nanometer tools to support 3-nanometer capacity in Tainan, and optimising flexible capacity across N7, N5, and N3 to extract more output from existing equipment. At the same time, Fab 2 (a 6-inch facility) and Fab 5 (an 8-inch facility focused on Gallium Nitride, a compound semiconductor) are being wound down, freeing physical space for leading-edge expansion. (LSEG StreetEvents 2026, p. 5)

 

Arizona: US$165 Billion and the Largest FDI in US History

Building on an existing US$65 billion commitment for the three-phase Fab 21 campus, TSMC announced in March 2025 an additional US$100 billion investment — bringing the total planned US commitment to US$165 billion. The expansion adds three new fabrication plants, two advanced packaging facilities, and a major R&D centre on a 1,100-acre site in North Phoenix, Arizona. TSMC described it as “the largest single foreign direct investment in US history.” The project is expected to create 40,000 construction jobs over four years and generate more than US$200 billion in indirect economic output over the following decade. Named customers for the Arizona site include Apple, Nvidia, AMD, Broadcom, and Qualcomm. (Taiwan Semiconductor Manufacturing Company Limited 2025a)

 

The three phases of Fab 21 are progressing on schedule. Phase 1 (N4 process) entered high-volume production at end-2024. Phase 2 (N3) has completed construction and targets volume production in H2 2027. Phase 3 (N2/A16) broke ground in 2025; an additional parcel of land was acquired in 2026 for subsequent phases. The US Department of Commerce, under the 2022 CHIPS Act, agreed to award TSMC Arizona up to US$6.6 billion in direct grants and up to US$5 billion in government loans, signed in November 2024. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4; LSEG StreetEvents 2026, p. 5)

 

Capital Expenditure Escalation (NT$ billions, FY2023–FY2026E)

 

Sources: TSMC 2026c, Item 5 (FY2023–2025 actuals in NT$); LSEG StreetEvents 2026, p. 4 (FY2026E: US$52–56B guidance converted at NT$31.7/US$). FY2026E midpoint = NT$1,712B. FY2025 USD equivalent: US$40.9B (stated in 20-F).

Japan and Germany: Completing the Three-Continent Footprint

Global New Fab Construction and Production Timeline

Facility	Location	Node	Application	HVM Target	Status
Fab 21 Ph. 1	Arizona, USA	N4 (4 nm)	HPC / AI	Q4 2024	✓ In Production
JASM Fab 1	Kumamoto, Japan	28 nm	Image sensor, Automotive	Dec 2024	✓ In Production
New Tainan N3 fab	Tainan, Taiwan (GIGAFAB)	N3 (3 nm)	AI / HPC / HBM base dies	H1 2027	Under construction
Fab 21 Ph. 2	Arizona, USA	N3 (3 nm)	HPC / AI (US customers)	H2 2027	Construction complete; equipping
JASM Fab 2	Kumamoto, Japan	N3 (3 nm)	Automotive / HPC	2028	Under construction (Oct 2025)
Fab 21 Ph. 3	Arizona, USA	N2 / A16	HPC / AI (next gen)	TBD	Construction started 2025
ESMC Fab 24	Dresden, Germany	Mature nodes	Automotive, Industrial	TBD	Construction started 2024

Sources: TSMC 2026c, Item 4 (Fab 21, JASM, ESMC status and ownership); LSEG StreetEvents 2026, pp. 5–6 (N3 expansion announcements, Arizona second land parcel).

In Kumamoto, Japan, TSMC’s majority-owned joint venture Japan Advanced Semiconductor Manufacturing (JASM — TSMC 72.6%, with Sony, DENSO, and Toyota as minority partners) began volume production at Fab 23 in December 2024, using 28-nanometer processes for image sensors and automotive chips. A second JASM fab, now upgraded to 3-nanometer technology, broke ground in October 2025 with volume production scheduled for 2028. In Dresden, Germany, the European Semiconductor Manufacturing Company (ESMC — TSMC 70.0%, with Bosch, Infineon, and NXP each holding 10%) is constructing Fab 24 for automotive and industrial chips. Production has not yet commenced. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4)

 

TSMC Process Roadmap — N3E Reference Baseline

Node	Transistor Type	Volume Production	Key Improvement vs. Prior Generation
N3P / N3A	FinFET (final mature stage)	2024–2026	5% speed or 5–10% power vs N3E; N3A: automotive certification 2026
N2	GAA Nanosheet (1st gen)	Q4 2025 (HVM)	10–15% speed or 20–30% power vs N3E; 1.15× density
N2P / N2U	GAA Nanosheet (enhanced)	N2P: H2 2026; N2U: 2028	Mobile/client performance focus; N2U: cost-efficient die shrink
A16	GAA + Backside Power	2027 (customer ramp adjusted)	8–10% speed or 15–20% power vs N2P; backside power delivery debuts
A14	GAA Nanosheet (2nd gen)	2028 (scheduled)	Full-node jump: 10–15% speed or 25–30% power; 20% density vs N2
A12 / A13	A14 platform extensions	2029 (scheduled)	A12: HPC/data centre power optimisation; A13: optical die shrink, A14 design compatible

Sources: Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 4; LSEG StreetEvents 2026, pp. 5–6. Columns marked “scheduled” are management guidance, not confirmed production.

Terms Explained

 

N2 / Gate-All-Around (GAA). TSMC's 2-nanometer process, and its first to use GAA nanosheet transistors. In a FinFET transistor, the gate electrode controls three sides of the current channel (a vertical 'fin'). In a GAA design, the current channel is a stack of thin horizontal sheets; the gate electrode wraps entirely around each sheet on all four sides. This gives far better electrical control, allowing lower voltage operation and hence lower power consumption and heat generation.

 

A14 / A16 (Angstrom-class nodes). Process generations beyond N2, named in angstroms (10⁻¹⁰ metres) rather than nanometres as a naming convention. A16 adds a backside power delivery network — routing supply current through the bottom of the chip wafer rather than competing with signal wiring on the front. A14 uses second-generation nanosheet transistors for a full-node performance step from N2. Volume production for A14 is scheduled for 2028.

 

US CHIPS Act. The CHIPS and Science Act of 2022, which authorised US$52.7 billion in US federal funding to encourage domestic semiconductor manufacturing. TSMC Arizona signed a Direct Funding Agreement for up to US$6.6 billion in grants and up to US$5 billion in loans from the Department of Commerce in November 2024. The grants require TSMC to meet certain domestic investment and workforce targets.

 

JASM / ESMC. Japan Advanced Semiconductor Manufacturing (JASM) is TSMC's majority-owned joint venture in Kumamoto, Japan (TSMC 72.6%, with Sony, DENSO, and Toyota as minority partners), operating Fab 23 and constructing a second fab. The European Semiconductor Manufacturing Company (ESMC) is TSMC's majority-owned joint venture (70.0%) in Dresden, Germany, with Bosch, Infineon, and NXP each holding 10%, constructing Fab 24 for automotive and industrial chips.

 

HBM Base Die. High Bandwidth Memory (HBM) is a type of computer memory used in AI servers. It consists of multiple memory chips stacked on top of each other like a tower. At the base of that tower is the 'base die' — a logic chip that manages communication between the memory layers and between the memory stack and the AI processor it connects to. As AI training systems use more and more memory, demand for HBM base dies (manufactured by TSMC on N3) has grown sharply.

 

V.  Principal Risks▶

V. Principal Risks: Trade Policy, Export Controls, and Geopolitical Concentration

Trade Policy Uncertainty

US Section 232 tariff (25%) on advanced chips; Section 301 investigations targeting Taiwan; US-Taiwan bilateral deal at 15% cap not yet finalised

 

Export Controls on China

VEU expired Dec 2025; replaced by fragile annual licence; China blocking statute creates legal cross-fire risk

 

Geopolitical Concentration

Majority of production facilities in Taiwan; any military escalation in the Taiwan Strait would threaten global chip supply

 

Customer Concentration

Top 10 customers = 78% of FY2025 revenue; largest = 19% (Apple); second largest = 17% (Nvidia)

 

Margin Dilution (Near-Term)

N2 ramp: 2–3% full-year GM dilution 2026; overseas fabs: 2–3% early-stage, 3–4% later-stage

 

I. Trade Policy: Section 232, Section 301, and the Bilateral Agreement

The most operationally immediate external risk is the rapidly changing US trade policy environment. In plain terms: the United States is restructuring the rules that govern where advanced chips can be made, shipped, and sold. A Section 232 investigation — a US law allowing the president to impose trade restrictions on national security grounds — into semiconductor imports concluded in December 2025. The result was a 25% tariff on certain advanced computing chips imported into the United States, accompanied by a tariff-offset programme that rewards companies investing in US domestic manufacturing. TSMC’s Arizona commitment is structured precisely to qualify for this offset. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3)

 

A separate broad tariff regime imposed in April 2025 was declared unlawful by the US Supreme Court in February 2026 and replaced under different legal authority. In March 2026, the US Trade Representative launched two new investigations under Section 301 — a different law covering unfair trade practices — explicitly naming Taiwan as a target, citing alleged manufacturing overcapacity and forced labour concerns. In January 2026, the US and Taiwan announced a bilateral trade agreement capping US tariff rates on Taiwanese goods at no more than 15%, with preferential treatment for Taiwanese semiconductor manufacturers investing in US capacity — but the details remain to be finalised. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3)

 

II. Export Controls: The Nanjing Licence Problem

TSMC operates a 16-nanometer fab in Nanjing, China (Fab 16). US regulations imposed since 2022 require individual licences for shipments of advanced semiconductor equipment to certain destinations. Until December 2025, TSMC Nanjing held a “Validated End-User” (VEU) authorisation, which allowed it to receive US-origin equipment without obtaining a licence for each shipment. That VEU expired in December 2025. The US Department of Commerce subsequently granted an annual export licence as a replacement, ensuring uninterrupted operations in the near term — but the Form 20-F states plainly: “there is no assurance that this annual export licence will not be terminated, or we can timely get the licence renewed in the future.” (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3)

 

China’s blocking statute — a law allowing Chinese entities to seek compensation from companies whose compliance with foreign laws causes them harm — creates a legal cross-fire. If TSMC reduces Nanjing operations to comply with US export controls, Chinese entities could potentially sue for damages under Chinese law. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3)

 

III. Geopolitical Concentration in Taiwan

The Form 20-F acknowledges this risk directly: “The majority of our principal executive officers and our principal production facilities are located in the R.O.C., and the majority of our net revenue is derived from our operations in the R.O.C.” The filing further notes: “the financial markets have viewed certain past developments in relations between the R.O.C. and the P.R.C. as occasions to depress general market prices of the securities of R.O.C. companies, including our own.” The ongoing geographic diversification — Arizona, Japan, Germany — is in part a strategic response to this risk, but TSMC also acknowledges that cross-border personnel restrictions may weaken some of the operational synergies that make Taiwan the centre of its cost and technology leadership. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3)

 

IV. Customer Concentration

TSMC’s top 10 customers accounted for 78% of FY2025 net revenue, up from 76% in FY2024 and 70% in FY2023. The largest single customer (Apple) represented 19% of revenue; the second-largest (Nvidia) 17%. At December 31, 2025, the top 10 customers accounted for 84% of accounts receivable. This concentration is a structural consequence of the AI-driven consolidation of semiconductor demand around a small number of hyperscale cloud operators and their chip suppliers. The risk is not that these customers are financially fragile; the risk is that their ordering patterns can shift rapidly as AI architectures evolve — a point C.C. Wei acknowledged directly when discussing the shift from generative AI to agentic AI and its implications for compute demand. (Taiwan Semiconductor Manufacturing Company Limited 2026c, Item 3; LSEG StreetEvents 2026, p. 5)

 

Customer Concentration Trend: Top 10 as % of Net Revenue

 

Source: TSMC 2026c, Item 3 (Risk Factors). Top 10 customers as % of annual net revenue. FY2025: largest customer 19%, second-largest 17%.

V. Near-Term Margin Dilution

Two known forces will dilute gross margin in 2026. First, the ramp-up of N2 production: as N2 volume scales in H2 2026, the heavy initial depreciation and yield learning costs of a brand-new process will weigh on margins. Wendell Huang, CFO, guided a 2–3% gross margin dilution for the full year of 2026. Second, overseas fab costs: operating factories in Arizona, Japan, and Germany is structurally more expensive than operating equivalent capacity in Taiwan, due to higher construction costs, labour costs, and regulatory compliance. Management has guided 2–3% dilution in the early stages of overseas expansion, widening to 3–4% in the later stages as more overseas fabs ramp up. (LSEG StreetEvents 2026, p. 4)

 

A supply-chain dimension was also flagged at the Q1 2026 call: the situation in the Middle East was identified as a potential source of price increases for specialty chemicals and gases, including helium and hydrogen, used in chip manufacturing. Management judged it too early to quantify the impact but noted that TSMC uses multi-source supply strategies for specialty materials and holds safety stock to buffer near-term disruptions. The longer-term picture remains constructive: N3 gross margin is expected to cross the corporate average in H2 2026, and management reaffirmed the long-term target of 56% gross margin and higher through the semiconductor cycle. (LSEG StreetEvents 2026, pp. 4–5)

 

Terms Explained

 

Section 232 (Trade Expansion Act of 1962). A US federal statute allowing the president to impose tariffs on imports that threaten national security. The December 2025 Section 232 determination applied a 25% tariff on certain advanced computing chip imports, with an offset programme for companies investing in US domestic production. TSMC's Arizona commitment is designed to qualify for this offset.

 

Validated End-User (VEU). A US Bureau of Industry and Security authorisation allowing a specific foreign facility to receive US export-controlled equipment and technology without obtaining an individual licence for each shipment. TSMC Nanjing's VEU expired in December 2025 and was replaced with a more fragile annual export licence requiring annual renewal by the Department of Commerce.

 

Section 301 (Trade Act of 1974). A US law allowing the US Trade Representative to investigate and retaliate against foreign trade practices deemed unfair or discriminatory. In March 2026, two Section 301 investigations were launched specifically targeting Taiwan, citing alleged overcapacity in manufacturing and forced labour practices.

 

Geopolitical Discount. The reduction in a company's market valuation that investors apply because of political or military risk in the country where the company operates. Past incidents of cross-strait tension between Taiwan and mainland China have caused TSMC's share price to fall, even when the company's financial performance was unaffected, because investors priced in a higher probability of disruption.

 

Margin Dilution. A reduction in a profitability ratio caused by adding revenue or capacity that is less profitable than the existing average. TSMC's overseas fabs and new N2 process both contribute revenue, but at a lower margin than established Taiwan-based N3 and N5 production — so their addition 'dilutes' (lowers) the consolidated gross margin average.

 

Source Credibility and Tier Classification

Source	Tier	Grade	Evidentiary Note
LSEG StreetEvents: Edited Transcript, Q1 2026 TSMC Earnings Call (Apr 16, 2026)	Tier 3 — LSEG StreetEvents	A−	Edited transcript of primary TSMC corporate event. LSEG is a globally recognised financial data service. LSEG's own disclaimer notes possible transcription inaccuracies; pull-quotes locked to supplied text. User-supplied PDF, session-processed.
TSMC 2025a: Form 6-K, Arizona Expansion (Mar 3, 2025)	Tier 1 — SEC EDGAR	A+	Primary corporate disclosure; fetch-verified. Source for US$165B figure, fab count, economic impact, and verbatim C.C. Wei statement.
TSMC 2026a: Form 6-K EX-99.2, Q4 2025 Earnings Presentation (Jan 15, 2026)	Tier 1 — SEC EDGAR	A+	Fetch-verified. Source for 2024–2029 revenue CAGR (~25%), long-term GM (56%+), and ROE (high-20s%) guidance.
TSMC 2026b: Form 6-K EX-99.2, Q1 2026 Earnings Presentation (Apr 16, 2026)	Tier 1 — SEC EDGAR	A+	Fetch-verified. Source for Q1 2026 platform revenue breakdown, balance sheet, and cash flow statement.
TSMC 2026c: Annual Report on Form 20-F FY2025 (Apr 16, 2026)	Tier 1 — SEC EDGAR	A+	Definitive annual disclosure. User-supplied PDF; full text extracted via pdftotext (122 pages). Primary source for all FY2025 financial data, business description, risk factors, and subsidiary details.
TSMC 2026d: Form 6-K, May 2026 Board Resolutions (May 12, 2026)	Tier 1 — SEC EDGAR	A+	Fetch-verified. Source for Q1 2026 board-approved financials, US$31,284M capital approps, US$20B Arizona injection, and NT$7.00/share dividend.
TSMC 2026e: Form 6-K EX-99.1, Q1 2026 Earnings Release (Apr 16, 2026)	Tier 1 — SEC EDGAR	A+	Fetch-verified. Source for Q1 2026 P&L table, technology node wafer revenue mix, Q2 2026 guidance, and operational statistics.

Bibliography

All citations follow Chicago Author-Date (17th edition). Sources are arranged alphabetically by institution, then by year and letter suffix.

LSEG StreetEvents. 2026. “Edited Transcript: 2330.TW — Q1 2026 Taiwan Semiconductor Manufacturing Co Ltd Earnings Call (Chinese, English).” Event date: April 16, 2026. Transcript ID: 16715184-2026-04-17T05:13:56.193. User-supplied PDF, session-processed, May 2026.

Taiwan Semiconductor Manufacturing Company Limited. 2025a. “TSMC Intends to Expand Its Investment in the United States to US$165 Billion to Power the Future of AI.” Form 6-K. Filed with SEC, March 3, 2025. SEC EDGAR accession 000104617925000024.

Taiwan Semiconductor Manufacturing Company Limited. 2026a. “2025 Fourth Quarter Earnings Conference.” Form 6-K, EX-99.2. Filed with SEC, January 15, 2026. SEC EDGAR accession 000104617926000008.

Taiwan Semiconductor Manufacturing Company Limited. 2026b. “2026 First Quarter Earnings Conference.” Form 6-K, EX-99.2. Filed with SEC, April 16, 2026. SEC EDGAR accession 000104617926000199.

Taiwan Semiconductor Manufacturing Company Limited. 2026c. Annual Report on Form 20-F for the Fiscal Year Ended December 31, 2025. Filed with SEC, April 16, 2026. Commission File No. 1-14700. [User-supplied PDF; navigate via: SEC EDGAR CIK 0001046179.]

Taiwan Semiconductor Manufacturing Company Limited. 2026d. “TSMC Board of Directors Meeting Resolutions.” Form 6-K. Filed with SEC, May 12, 2026. SEC EDGAR accession 000104617926000274.

Taiwan Semiconductor Manufacturing Company Limited. 2026e. “TSMC Reports First Quarter EPS of NT$22.08.” Form 6-K, EX-99.1. Filed with SEC, April 16, 2026. SEC EDGAR accession 000104617926000199.

Disclaimer. This briefing is an informational analysis based on publicly available primary sources and does not constitute investment advice. All figures are sourced from the referenced disclosures and subject to revision by subsequent filings.

Sources: SEC EDGAR (TSM Form 20-F FY2025; 6-K series 2025–2026) · LSEG StreetEvents Q1 2026 Earnings Call · Published May 2026